Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy

We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.

• Type: Conference
• Year: 2003
• Where: VLSID
• Authors: Vani Prasad, Madhav P. Desai
• Keywords: Computer Architecture, Simple Buffering Architecture, VLSI Circuit.The Problem, VLSID 2003, Wire Sizing Problem