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    DT
    2007
    57views more  DT 2007»
    Leakage Minimization Technique for Nanoscale CMOS VLSI
    14 years 6 months ago
    Leakage Minimization Technique for Nanoscale CMOS VLSI
    Download  www.ece.neu.edu
    This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
    Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Pa...
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    ASPDAC
    2007
    ACM
    95views Hardware» more  ASPDAC 2007»
    Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
    14 years 10 months ago
    Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
    Download  www.cecs.uci.edu
    Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
    Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
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