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TCAD
2002
139views more  TCAD 2002»
13 years 11 months ago
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters base...
In-Cheol Park, Hyeong-Ju Kang
TCAD
2002
110views more  TCAD 2002»
13 years 11 months ago
A constructive genetic algorithm for gate matrix layout problems
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
Alexandre César Muniz de Oliveira, Luiz Ant...
TCAD
2002
98views more  TCAD 2002»
13 years 11 months ago
Reporting of standard cell placement results
VLSI fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement appro...
Patrick H. Madden
TCAD
2002
88views more  TCAD 2002»
13 years 11 months ago
Estimating routing congestion using probabilistic analysis
Jinan Lou, Shashidhar Thakur, Shankar Krishnamoort...
TCAD
2002
91views more  TCAD 2002»
13 years 11 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
TCAD
2002
121views more  TCAD 2002»
13 years 11 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
TCAD
2002
146views more  TCAD 2002»
13 years 11 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
TCAD
2002
118views more  TCAD 2002»
13 years 11 months ago
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...