Sciweavers

TCAD
2010
121views more  TCAD 2010»
13 years 6 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
TCAD
2010
118views more  TCAD 2010»
13 years 6 months ago
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore
Abstract--Microfluidics-based biochips enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrat...
Krishnendu Chakrabarty, Richard B. Fair, Jun Zeng
TCAD
2010
90views more  TCAD 2010»
13 years 6 months ago
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration
The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
TCAD
2010
168views more  TCAD 2010»
13 years 6 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
TCAD
2010
98views more  TCAD 2010»
13 years 6 months ago
Statistical Modeling With the PSP MOSFET Model
PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV s...
Xin Li, Colin C. McAndrew, Weimin Wu, Samir Chaudh...
TCAD
2010
102views more  TCAD 2010»
13 years 6 months ago
Functional Test Generation Using Efficient Property Clustering and Learning Techniques
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
Mingsong Chen, Prabhat Mishra
TCAD
2010
110views more  TCAD 2010»
13 years 6 months ago
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Ha...
TCAD
2010
88views more  TCAD 2010»
13 years 6 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan