ISMVL
1999
IEEE
14 years 4 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
ISMVL
2006
IEEE
14 years 6 months ago
2006
IEEE
Abstract— This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it poss...