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    ISMVL
    2007
    IEEE
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    Fault Tolerant CMOS Logic Using Ternary Gates
    14 years 5 months ago
    Fault Tolerant CMOS Logic Using Ternary Gates
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    In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
    Yngvar Berg, Renè Jensen, Johannes Goplen L...
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