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    ICCAD
    2009
    IEEE
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    Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
    13 years 9 months ago
    Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
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    We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
    Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
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