Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical verification. Experimenting with the STARI circuits, the proposed approach shows its effectiveness.

• Type: Conference
• Year: 2004
• Where: ATVA
• Authors: Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
• Keywords: ATVA 2004, Timed Circuits, Timed Trace, Trace Theoretic Verification