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DAC
1994
ACM
14 years 3 months ago
HSIS: A BDD-Based Environment for Formal Verification
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin...
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
14 years 4 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim