DAC
1994
ACM
14 years 4 months ago
1994
ACM
DAC
1994
ACM
14 years 4 months ago
1994
ACM
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
ASYNC
2002
IEEE
14 years 5 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...