ICCD
2003
IEEE
14 years 8 months ago
2003
IEEE
This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...