TCAD
2010
13 years 5 months ago
2010
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
CAL
2004
13 years 10 months ago
2004
Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional lat...
ASPDAC
1995
ACM
14 years 2 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
ISPD
2004
ACM
14 years 4 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...