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    DAC
    2006
    ACM
    120views Computer Architecture» more  DAC 2006»
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
    15 years 15 days ago
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
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    Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
    Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
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