Symbolic noise analysis approach to computational hardware optimization

This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies. Categories and Subject Descriptors B.2 [Arithmetic and Logic Structures]: Performance Analysis and Design Aids General Terms Algorithms, Design Keywords Computational error, word-length optimization, high level synthesis, computer arithmetic

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Arash Ahmadi, Mark Zwolinski
• Keywords: Computational Error Modeling, DAC 2008, Design Automation, Keywords Computational Error, Trading Computational Error