Architecture Support for Improving Bulk Memory Copying and Initialization Performance

—Bulk memory copying and initialization is one of the most ubiquitous operations performed in current computer systems by both user applications and Operating Systems. While many current systems rely on a loop of loads and stores, there are proposals to introduce a single instruction to perform bulk memory copying. While such an instruction can improve performance due to generating fewer TLB and cache accesses, and requiring fewer pipeline resources, in this paper we show that the key to significantly improving the performance is removing pipeline and cache bottlenecks of the code that follows the instructions. We show that the bottlenecks arise due to (1) the pipeline clogged by the copying instruction, (2) lengthened critical path due to dependent instructions stalling while waiting for the copying to complete, and (3) the inability to specify (separately) the cacheability of the source and destination regions. We propose FastBCI, an architecture support that achieves the granular...

• Type: Conference
• Year: 2009
• Where: IEEEPACT
• Authors: Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar Iyer
• Keywords: Cache Bottlenecks, Hardware, IEEEPACT 2009, Memory Copying, —Bulk Memory Copying