A Visual Approach to Validating System Level Designs

This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual specification, as Live Sequence Charts (LSCs), of the properties to be checked. The LSCs are automatically translated into the input format for the SystemC-based checker engine, which indicates during simulation, if the property is fulfilled or produces a counter-example, if the property is violated. The entire process from the visual property specification to the checking is largely automated, which makes our approach accessible even for users which have not been trained in formal methods. Categories and Subject Descriptors I.6.4 [Simulation and Modeling]: Model Validation and Analysis General Terms Design, Verification Keywords Validation Methodology, Simulation, Sequence Charts

• Type: Conference
• Year: 2002
• Where: ISSS
• Authors: Jürgen Ruf, Thomas Kropf, Jochen Klose
• Keywords: Hardware, ISSS 2002, Keywords Validation Methodology, Live Sequence Charts, Sequence Charts