Thermal resilient bounded-skew clock tree optimization methodology

The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is further exacerbated by the aggressive scaling and other factors such as dynamic power management schemes and nonuniform gate level switching activity. In high-performance systems, one of the most important problems is clock skew minimization since it has a direct impact on the maximum operating frequency of the system. Since clocks are routed across the entire chip, the presence of thermal gradients can significantly alter their characteristics because wire resistance increases linearly as the temperature increases. This often results in failure to meet original timing constraints thereby rendering the original topology unusable. Therefore it is necessary to perform a temperature aware re-embedding of the original topology to meet timing under these temperature effects. This work primarily explores these i...

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
• Keywords: DATE 2006, Hardware, Non-uniform Thermal Gradients, Thermal Gradients, Timing Constraints