Power-constrained test scheduling for multi-clock domain SoCs

This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a test scheduling algorithm for multi-clock domain SoCs to minimize test time under power constraint. In the proposed method, we use virtual TAM to solve the frequency gaps between cores and the ATE, and also to reduce power consumption of a core during test while maintaining the test time of the core. Experimental results show the effectiveness of our method not only for multi-clock domain SoCs, but also for single-clock domain SoCs with power constraints.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
• Keywords: DATE 2006, Hardware, Multi-clock Domain Socs, Test Access Mechanism, Test Time