Power supply variation effects on timing characteristics of clocked registers

— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under VDD variations.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: William R. Roberts, Dimitrios Velenis
• Keywords: ISCAS 2006, Power Supply, Power Supply Voltage, Register Design