Hierarchical power distribution and power management scheme for a single chip mobile processor

A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU’s that is baseband processor, application processor, and multi-media processor. In the “waiting for calling” mode of the mobile handsets, application processor and multimedia processor part can be power-off. This chip can power off these power domains although the some of baseband parts are actively operating.. Many new techniques for multiple power domains in the chip are described. Categories and Subject Descriptors B.7.1 [Types and Design Styles]: General Terms: Design. Keywords VLSI, power domain, partial power off, mobile processor.

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
• Keywords: Application Processor, Chip Mobile Processor, Computer Architecture, DAC 2006, Power Domain