High-level synthesis for large bit-width multipliers on FPGAs: a case study

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource costeffectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluat...

• Type: Conference
• Year: 2005
• Where: CODES
• Authors: Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell
• Keywords: CODES 2005, Hardware-Software Codesign, Integer Multiplier Circuits, Integer Multiplier Units, Multiplier Units