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27

ISPASS
2005
IEEE

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Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors

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Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors

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Jian Li, José F. Martínez

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ISPASS 2005 | Software Engineering |

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Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	ISPASS
Authors	Jian Li, José F. Martínez

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