FinFET-based SRAM design

Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2x improvement in SNM can be achieved in 6-T FinFET-based SRAM cells, A 4-T PinFET-based SRAM cell with built-in feedback can achieve sub-1OOpA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractiveifor low-power, low-voltage applications. Categories and Subject Descriptors B.3.1 [Memory Structures]: Semiconductor Memories - Slutic memory (SRAM); 8.7.1 [Integrated Circuits]: Types and Design Styles -Advanced Technologies,Memov Technologies General Terms: Design

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic
• Keywords: 4-t Finfet-based Sram, FinFET-based SRAM Cells, ISLPED 2005, SRAM Cell