Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Law...
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...
Zheng Guo, Sriram Balasubramanian, Radu Zlatanovic...
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is redu...
—Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor wh...