Instruction set extension with shadow registers for configurable processors

Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) becomes a potential performance bottleneck. In this paper we first present a quantitative analysis of the data bandwidth limitation in configurable processors, and then propose a novel low-cost architectural extension and associated compilation techniques to address the problem. The application of our approach results in a promising performance improvement. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and application-based systems – microprocessor General Terms Algorithms, Design, Performance Keywords ASIP, configurable processor, shadow registe...

• Type: Conference
• Year: 2005
• Where: FPGA
• Authors: Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
• Keywords: Configurable Processor, Data Bandwidth, FPGA 2005, Hardware, Potential Performance Bottleneck