Floating-point sparse matrix-vector multiply for FPGAs

Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, it is not uncommon for microprocessors to yield only 10–20% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. For benchmark matrices from

• Type: Conference
• Year: 2005
• Where: FPGA
• Authors: Michael DeLorimier, André DeHon
• Keywords: FPGA 2005, Hardware, Local Distributed Memory, Peak floating-point Performance, Sparse Matrix-Vector