Automated synthesis for asynchronous FPGAs

We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Categories and Subject Descriptors

• Type: Conference
• Year: 2005
• Where: FPGA
• Authors: Song Peng, David Fang, John Teifel, Rajit Manohar
• Keywords: Asynchronous, FPGA 2005, Hardware, Logic Synthesis Method, Synthesis Method