Secure Logic Synthesis

This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Kris Tiri, Ingrid Verbauwhede
• Keywords: FPL 2004, Mere Doubling, Single Ended Implementation, Slice Utilization