Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders

In this paper, we motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13µm and 0.10µm CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.

• Type: Conference
• Year: 2003
• Where: ARITH
• Authors: Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
• Keywords: 64-bit Processor Adders, Applied Computing, ARITH 2003, Vlsi Adder, VLSI Adder Topologies