Micro-Network for SoC: Implementation of a 32-Port SPIN network

We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 Gbits/s. In a 6 metal process, all the routing wires can be routed on top of the switching components. The SPIN32 macro-cell will be fabricated by ST Microelectronics, but this macrocell uses symbolic layout, and can be manufactured with any CMOS process including 6 metal layers.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Adrijean Andriahantenaina, Alain Greiner
• Keywords: 32-ports Spin Micro-network, CMOS Process, DATE 2003, Hardware, Micron Cmos