Generalized Posynomial Performance Modeling

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with device-level accuracy. We will prove that this problem corresponds to solving a non–convex optimization problem without local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time–consuming nature of hand–crafted analytic model generation. Experimental results illustrate the capabilities and effectiveness of the presented modeling technique.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
• Keywords: Analog Integrated Circuits, Circuit Sizing Problem, DATE 2003, Hardware, Posynomial Symbolic Expressions