Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

1 We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of timetriggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Paul Pop, Petru Eles, Zebo Peng
• Keywords: Case Queuing Delay, DATE 2003, Hardware, Minimal Buffer Needs, Schedulability Analysis