A Quadruple Precision and Dual Double Precision Floating-Point Multiplier

Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this implementation, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have a latency of only two cycles. The design is pipelined so that two double precision multiplications can be started every cycle or a quadruple precision multiplication can be started every other cycle. Key words: Quadruple precision, double precision, multiplier, floating-point, computer arithmetic, rounding, normalization.

• Type: Conference
• Year: 2003
• Where: DSD
• Authors: Ahmet Akkas, Michael J. Schulte
• Keywords: Double Precision, DSD 2003, Hardware, Precision Multiplication, Quadruple Precision