GLVLSI
2003
IEEE
14 years 18 days ago
2003
IEEE
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper examines latch style voltage mode sense amplifiers for operation in the sub-threshold region, where VDD<VT. We show that the offset gets worse relative to strong inv...