PDL: A New Physical Synthesis Methodology

In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.

• Type: Conference
• Year: 2003
• Where: ISQED
• Authors: Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura
• Keywords: Hardware, ISQED 2003, Layout Quality, Physical Synthesis Methodology, Timing Quality