Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits

In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is based on partial duplication and show that it is capable of reducing the soft error failure rate significantly with a fraction of the overhead required for full duplication. A procedure for characterizing the soft error susceptibility of nodes in a logic circuit, and a heuristic procedure for selecting the set of nodes for partial duplication are described. A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Kartik Mohanram, Nur A. Touba
• Keywords: Hardware, ITC 2003, Soft Error, Soft Error Failure, Soft Error Susceptibility