FPGA Implementations of the RC6 Block Cipher

RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w , bitwise exclusive or of two w-bit words, rotation to the left, and computation of f(X) = (X(2X + 1)) mod 2w , which is the critical arithmetic operation of this block cipher. In this paper, we investigate and compare four implementations of the f(X) operator on Virtex-E and Virtex-II devices. Our experiments show that the choice of an algorithm is strongly related to the target FPGA family. We also describe several architectures of a RC6 processor designed for feedback or non-feedback chaining modes. Our fastest implementation achieves a throughput of 15.2 Gb/s on a Xilinx XC2V3000-6 device.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: Jean-Luc Beuchat
• Keywords: 128-bit Ciphertext Blocks, 128-bit Plaintext Blocks, FPL 2003, Integer Addition Modulo