A methodology for the characterization of process variation in NoC links

—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that could be sustained by each link that interconnects two cores in a chip multiprocessor. In this paper we present a methodology to model delay variations in NoC links. We also show its application to several technologies, namely 45nm, 32nm, 22nm, and 16nm. Simulation results show that conclusions about variability greatly depend on the implementation context.

• Type: Conference
• Year: 2010
• Where: DATE
• Authors: Carles Hernandez, Federico Silla, José Duato
• Keywords: Chip Multiprocessor, DATE 2010, Hardware, Integration Scales, Process Variability