Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal control is required because of temperature impact on leakage and reliability. To be effective, the implementation of these policies involves decisions that must be taken during various phases along the design process, to enable the development of architectural level countermeasures and the required hardware knobs, such as power modes, power supply regulation granularity and the number of on-chip temperature sensors. As a consequence, a framework allowing thermal estimation exploiting design-time information is desirable. In this paper we propose a solution on this direction, by presenting an integrated estimation environment for the evaluation of chip temperature profiles. It exploits heterogeneous power information available during the design phase. Power information is used to drive a thermal simulation engine ...