Congestion Estimation with Buffer Planning in Floorplan Design

In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that a net will pass through each particular location of a floorplan taken into account buffer locations and routing blockages. Experimental results show that our congestion model can optimize congestion and delay (by successful buffer insertions) of a circuits better with only a slight penalty in area.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young
• Keywords: Account Buffer Locations, Buffer Block Planning, DATE 2002, Hardware, Successful Buffer Insertions