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ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
14 years 4 months ago
Vector instruction set support for conditional operations
Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementation...
James E. Smith, Greg Faanes, Rabin A. Sugumar
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
14 years 4 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
14 years 4 months ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 4 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 4 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ISCA
2000
IEEE
97views Hardware» more  ISCA 2000»
14 years 4 months ago
Energy-driven integrated hardware-software optimizations using SimplePower
Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary ...
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
14 years 4 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 4 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
14 years 4 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ISCA
2000
IEEE
94views Hardware» more  ISCA 2000»
14 years 4 months ago
A hardware mechanism for dynamic extraction and relayout of program hot spots
Matthew C. Merten, Andrew R. Trick, Erik M. Nystro...