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ASPDAC
1999
ACM

Relaxed Simulated Tempering for VLSI Floorplan Designs

14 years 3 months ago
Relaxed Simulated Tempering for VLSI Floorplan Designs
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy landscape with many local minima separated by high energy barriers. In this paper, we have successfully applied a version of relaxed simulated tempering to slicing floorplan design with consideration of both area and wirelength optimization. Good experimental results were obtained.
Jason Cong, Tianming Kong, Dongmin Xu, Faming Lian
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where ASPDAC
Authors Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong
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