Channel-Based Behavioral Test Synthesis for Improved Module Reachability

We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of transparency channels, test justification and propagation bottlenecks are revealed for each module in the design. Subsequently, the proposed behavioral test synthesis scheme eliminates, during scheduling, allocation and binding, as many reachability bottlenecks, as possible. Furthermore, it identifies the control states and provides the templates required for translating each module's test into global design test. We demonstrate our scheme on a representative example, unveiling the potential of path analysis based techniques to accurately identify and eliminate module reachability bottlenecks, thus guiding behavioral test synthesis.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Yiorgos Makris, Alex Orailoglu
• Keywords: Behavioral Test Synthesis, DATE 1999, Hardware, Module Reachability, Reachability Bottlenecks