At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks

As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on boardlevel interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Jongchul Shin, Hyunjin Kim, Sungho Kang
• Keywords: At-speed Solution, Boundary-scan Cells, DATE 1999, Enhanced Boundary-scan Architecture, Hardware