On Programmable Memory Built-In Self Test Architectures

The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more e cient and exible than existing architectures. Test logic overhead of the proposed programmable versus non-programmable memory BIST architectures is evaluated. The proposed programmable memory BIST architectures could be used to test memories in di erent stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and exibility while having less test logic overhead than the programmable FSM-based memory BIST architecture.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Kamran Zarrineh, Shambhu J. Upadhyaya
• Keywords: DATE 1999, Hardware, Memory Bist, Memory Bist Architecture, Microcode-based Memory Bist