Performance optimization under rise and fall parameters

Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performance optimization algorithms, however, assume a single value for each parameter. No work has been done to study the impact of separate rise and fall values on the complexity of optimization. In this paper, we take the rst step towards understanding this impact. We pick two problems that have polynomial-time complexitiesif a singlevalue for eachcell parameteris assumed. The rst problemis that of bu erinsertionon a xed topologynet to maximizethe requiredtime at the source of the net. The second is the gate resizing problem and the more general technology mapping problem for minimizing the circuit delay under the simplest, load-independent delay model. We show that under separate rise and fall parameters, both these problems become NP-complete. To the best of our knowledge,this is the rst such result showing the e...

• Type: Conference
• Year: 1999
• Where: ICCAD
• Authors: Rajeev Murgai
• Keywords: Delay Model, Hardware, ICCAD 1999, Input Pin, Load-independent Delay Model