Dynamic trellis diagrams for optimized DSP code generation

In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal processors (DSPs). In contrast to static trellis diagrams (STDs), which may be precalculated, DTDs are built at runtime and adapted exactly to the local requirements. Therefore, DTDs are more flexible and need less program memory. Due to the significant reduction in memory size, the increase of compilation time is only moderate. At present, the concept of DTDs has been successfully applied to DFG compiler implementations for a variety of general purpose DSP families, including Motorola's DSP56000 and Analog Devices' ADSP2100.

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: Stefan Fröhlich, Martin Gotschlich, Udo Krebelder, B. Wess
• Keywords: Dynamic Trellis Diagrams, Hardware, ISCAS 1999, Static Trellis Diagrams, Trellis Diagrams