Efficient Scheduling of DSP Code on Processors with Distributed Register Files

Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in this paper analyses the combination of limited register file capacity, resource- and timing constraints during scheduling. Value lifetimes are serialized until all capacity constraints are guaranteed to be satisfied after scheduling. Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for innermost loops of DSP algorithms.

• Type: Conference
• Year: 1999
• Where: ISSS
• Authors: Bart Mesman, Carlos A. Alba Pinto, Koen Van Eijk
• Keywords: Capacity Constraints, Hardware, ISSS 1999, Tight Timing Constraints, Timing Constraints