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ASPDAC
1998
ACM

An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits

14 years 3 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming-based algorithm, SiMPA-D, used for performing simultaneous technology mapping and linear placement of logic clusters. This algorithm generates a set of solutions for each cluster, all of which are noninferior (in terms of gate area, cutwidth and delay), and hence permits trade-offs between total area (gate plus wiring) and total delay (gate plus wiring). Experimental results from a large number of MCNC benchmarks have proved the effectiveness of the proposed flow.
Jinan Lou, Amir H. Salek, Massoud Pedram
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ASPDAC
Authors Jinan Lou, Amir H. Salek, Massoud Pedram
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