On wirelength estimations for row-based placement

Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniques appropriate for wirelength estimation during topdown oorplanning and placement of cell-based designs. Our methods give accurate, linear-time approaches, typically with sublinear time complexity for dynamic updating of estimates e.g., for annealing placement. Our techniques o er advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a nal placement. In developing these new estimators, we have made several contributions, including i insight into the contrast between region-based and bounding box-based RStMT estimation techniques; ii empirical assessment of the correlations between pin placements of a multi-pin net that is contained in a block; and iii new wirelength estimates that are functions of a block&...

• Type: Conference
• Year: 1998
• Where: ISPD
• Authors: Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
• Keywords: Estimation Techniques, Hardware, ISPD 1998, Wirelength Estimation, Wirelength Estimation Techniques