We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
With the recent advent of deep sub-micron technology and new packaging schemes such as Multi-Chip Modules(MCMs), integrated circuit components are often not rectangular. Most exis...
In this paper, we present a performance-driven softmacro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also pr...
We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeata...
Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojw...
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit d...
This paper proposes a placement method for a mixed set of hard, soft, and pre-placed modules, based on a placement topology representation called sequence-pair. Under one sequence...
In this paper, we formulate the problem of topology constrained rectilinear block packing in layout reuse. A speci c class of rectilinear shaped blocks, ordered convex rectilinear...
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Huij...